Most signals in the world in which we live are analog, i.e., cover a continuous range of amplitude values. However, most computer systems for processing these signals are binary digital systems. Generally, synchronous analog-to-digital (A/D) converters are used to capture analog signals and present a digital approximation of the input signal to a computer processor. That is, at precise moments in time synchronized to a system clock, the amplitude of the signal of interest is captured as a digital value. When sampling the amplitude of an analog signal, each bit in the digital representation of the signal represents an increment of voltage, which defines the resolution of the A/D converter. Analog-to-digital conversion is used in numerous applications, such as communications where a signal to be communicated may be converted from an analog signal, such as voice, to a digital signal prior to transport along a transmission line. Applying traditional sampling theory, a band limited signal can be represented with a quantifiable error by sampling the analog signal at a sampling rate at or above what is commonly referred to as the Nyquist sampling rate.
While traditional A/D conversion techniques have been effective, techniques based on amplitude sampling have limitations. For example, it has been a continuing trend in electronic circuit design to reduce the available operating voltage provided to integrated circuit devices. In this regard, over the last decade, power supply voltages have decreased from five volts to three volts and there remains a desire to reduce this further, such as to one volt or less. While digital signals can be readily processed at the lower supply voltages, traditional synchronous sampling of the amplitude of a signal becomes more difficult as the available power supply voltage is reduced and each bit in the A/D or D/A converter reflects a substantially lower voltage increment. Thus, there remains a need to develop circuits and methods for performing high resolution A/D and D/A conversion using substantially lower power supply voltages which will be desired in future designs.
In contrast to sampling a signal using synchronous A/D converters, circuits are known for performing asynchronous time encoding of a signal. One such circuit, referred to as an asynchronous sigma delta modulator (ASDM) is disclosed in U.S. Pat. No. 6,087,968 to Roza (“the '968 patent”). An example of such an ASDM is illustrated herein in FIG. 1. The ASDM generates an asynchronous duty cycle modulated square wave at output z(t) which is representative of the input signal, x(t). In the '968 patent, an ASDM is used to form an analog-to-digital converter by providing the output of the ASDM to a sampler and a linear decimating filter which is sampled at a rate above the bandwidth of the input signal. A problem with this approach is that the ASDM introduces non-linearities in z(t) which cannot be recovered using a linear decimation filter. As a result, the degree of signal recovery is limited. Another shortcoming with this approach is that the output of the ASDM must be over sampled by a high frequency clock. As the bandwidth of the input signal increases, the clock frequency also increases. Even if the desired clock rate can be achieved, such high frequency clocks demand significant power consumption.
While the '968 patent discloses the use of an ASDM to time encode an analog signal, certain characteristics of the ASDM circuit were not previously appreciated. For example, the '968 patent does not disclose a method of designing the ASDM in order to have the ASDM output signal be fully invertible, i.e., allow for theoretically perfect recovery of the input signal. Further, the '968 patent does not disclose that the ASDM is a non-linear system and that a non-linear recovery method is required to fully take advantage of this circuit.